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CHIPSEL.LST
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1990-05-02
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681 lines
Motorola 68000 Family Assembler (1.0 ) Wed May 02 21:07:02 1990
M68332 BUSINESS CARD COMPUTER CHIP SELECT INIT
abs. rel. LC obj. code source line
---- ---- ---- --------- -----------
1 1 0000 | TTL M68332 BUSINESS CARD COMPUTER CHIP SELECT INIT
2 2 0000 | OPT P=68332 SETUP FOR 68332 CODE
3 3 0000 | OPT BRS SHORT BRANCHES PREFERED
4 4 0000 |
5 5 0000 |******************************************************************************
6 6 0000 |*** EXPORTED PORTION OF THE MODULE HEADER ***
7 7 0000 |*V****************************************************************************
8 8 0000 |******************************************************************************
9 9 0000 |*** ***
10 10 0000 |*** MODULE : CHIP SELECT INITIALIZATION ***
11 11 0000 |*** ***
12 12 0000 |*** ENVIRONMENT : 68332 Business Card Computer (BCC) Rev. A, B ***
13 13 0000 |*** For M68332PFB Platform Board, Rev. A, B, C ***
14 14 0000 |*** ***
15 15 0000 |*** NOTE: BCC Rev. A + PFB Rev. A = Old System ***
16 16 0000 |*** BCC Rev. B + PFB Rev. B = New System ***
17 17 0000 |*** ***
18 18 0000 |*** PFB Rev. C is jumper selectable to be function- ***
19 19 0000 |*** ally equivalent to Rev. A or to Rev. B. ***
20 20 0000 |*** ***
21 21 0000 |*** ---- DO NOT MIX REV. A's WITH REV. B's! ---- ***
22 22 0000 |*** ---- NO STACK USAGE (SUBR'S) ALLOWED! ---- ***
23 23 0000 |*** ***
24 24 0000 |*** LANGUAGE : 68332 ASSEMBLY LANGUAGE ***
25 25 0000 |*** ***
26 26 0000 |*** SUMMARY OF CONTENTS : ***
27 27 0000 |*** Determines BCC type (A or B) and initializes the appropriate chip ***
28 28 0000 |*** selects using the corresponding values from the parameter area. ***
29 29 0000 |*** ***
30 30 0000 |*** LINK REQUIREMENTS : ***
31 31 0000 |*** NOTES: ***
32 32 0000 |*** 1. Source equivalent copy of 332Bug parameter area for Motorola ***
33 33 0000 |*** FREEWARE Bulletin Board System (BBS) to produce object ***
34 34 0000 |*** equivalent code. See REVISION HISTORY below for version nbr. ***
35 35 0000 |*** 2. This source code can be freely used at no cost/obligation, ***
36 36 0000 |*** i.e. it is PUBLIC DOMAIN software. Please report any errors/ ***
37 37 0000 |*** additions to the SYSOP of the Motorola FREEWARE BBS. ***
38 38 0000 |*** 3. Parameters which reference linker symbols (XREF/XDEF) will ***
39 39 0000 |*** not be defined until link time, so the obj. code listed here ***
40 40 0000 |*** will not match the actual EPROM code. ***
41 41 0000 |*** ***
42 42 0000 |******************************************************************************
43 43 0000 |*^****************************************************************************
44 44 0000 |*
45 45 0000 | PAGE
46 46 0000 |*
47 47 0000 |******************************************************************************
48 48 0000 |*** INTERNAL PORTION OF THE MODULE HEADER ***
49 49 0000 |******************************************************************************
50 50 0000 |*** ***
51 51 0000 |*** REVISION HISTORY (add changes to the top): ***
52 52 0000 |*** ***
53 53 0000 |*** DATE AUTHOR CHANGES ***
54 54 0000 |*** ---------- --------------- ------------------------------------- ***
55 55 0000 |*** 01/17/90 Peter S. Gilmour Initial version port to MS_DOS based ***
56 56 0000 |*** M68MASM from original source code. ***
57 57 0000 |*** Compatible with 332Bug version 1.01. ***
58 58 0000 |*** 05/02/90 Peter S. Gilmour Compatible with 332Bug version 1.02. ***
59 59 0000 |******************************************************************************
60 60 0000 |*** XDEFS : ***
61 61 0000 | XDEF INIT_CS
62 62 0000 |*** ***
63 63 0000 |*** XREFS : ***
64 64 0000 | XREF PWR_TTL
65 65 0000 | XREF .RAMMCR
66 66 0000 | XREF .RAMBAR
67 67 0000 | XREF .CSBAR0,.CSBAR1,.CSBAR2,.CSBARBT
68 68 0000 | XREF CSBAR0$
69 69 0000 |*** ***
70 70 0000 |*** Local macros: ***
71 71 0000 |*** ***
72 72 0000 |SYSTEM MACRO ! SETUP MONITOR SPACE
73 73 0000 |SECTD SET 1 ! DEFINE DATA SECTION
74 74 0000 |SECTP SET 14 ! DEFINE PROGRAM SECTION
75 75 0000 | SECTION SECTP ! PUT USER INTO PROG. SECTION
76 76 0000 | ENDM !
77 77 0000 |*
78 78 0000 |* Time delay macro
79 79 0000 |* - allows bus capacitance to dissipate
80 80 0000 |* - at least 3 words must be fetched to guarantee dissipation
81 81 0000 |*
82 82 0000 |T_DELAY MACRO
83 83 0000 | NOP
84 84 0000 | NOP
85 85 0000 | NOP
86 86 0000 | ENDM
87 87 0000 |
88 88 0000 |***
89 89 0000 |*** Local equates:
90 90 0000 |***
91 91 0000 0000 |OLD_BCC EQU 0 Code ID for old BCC
92 92 0000 0001 |NEW_BCC EQU 1 Code ID for new BCC
93 93 0000 |
94 94 0000 |*
95 95 0000 |* For M68332 BCC and PFB.
96 96 0000 |*
97 97 0000 |* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
98 98 0000 |* addressing (sign extension) can be used.
99 99 0000 |*
100 100 0000 2700 |SR_VAL EQU $2700 status register initial value.
101 101 0000 |
102 102 0000 0000 |RAM_BASE EQU $0 BCC RAM base address
103 103 0001 0000 |RAM_SIZE EQU $10000 BCC RAM size (bytes)
104 104 0006 0000 |ROM1_BASE EQU $60000 BCC EPROM base address
105 105 0002 0000 |ROM1_SIZE EQU $20000 BCC EPROM size (bytes)
106 106 0004 0000 |IRAM_BASE EQU $40000
107 107 FFFF E800 |FPCP_BASE EQU $FFFFE800 PFB MC68881/MC6882 base address
108 108 0000 |* . (Floating Point Co-Processor)
109 109 FFFF FA00 |SIM EQU $FFFFFA00 BCC M68332 System Integration Module base addr
110 110 FFFF FB00 |RAMCR EQU $FFFFFB00 BCC M68332 RAM Control Module base address
111 111 FFFF F800 |AUTO_BASE EQU $FFFFF800 Autovector base address
112 112 0000 |
113 113 0000 0000 |LOCALRAM EQU RAM_BASE base of local RAM
114 114 0000 4000 |SYSRAMSZ EQU $00004000 size of local RAM (for system use)
115 115 0001 0000 |LCLRAMMX EQU RAM_SIZE max size of local RAM (for M68332 BCC)
116 116 0000 4000 |USRRAM EQU LOCALRAM+SYSRAMSZ base of user RAM
117 117 0000 C000 |USRRAMSZ EQU LCLRAMMX-SYSRAMSZ size of user RAM
118 118 0000 0000 |RAMSTART EQU LOCALRAM alias for base of local RAM
119 119 0000 |
120 120 0006 0000 |LOCALROM EQU ROM1_BASE base of local ROM (use PC rel refs!)
121 121 0001 0000 |LCLROMSZ EQU $00010000 size of local ROM used by 332Bug
122 122 0000 00FF |ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
123 123 0000 00FF |FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
124 124 0000 FFFF |FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
125 125 FFFF FFFF |FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
126 126 0000 |
127 127 0001 0000 |RAM2_BASE EQU LOCALRAM+LCLRAMMX Next RAM base address
128 128 0008 0000 |ROM2_BASE EQU ROM1_BASE+ROM1_SIZE Next ROM base address
129 129 0000 |
130 130 0000 0400 |VECTSIZ EQU $400 Vector table size
131 131 0000 1000 |USERLEN EQU $1000 user space reserved
132 132 0000 4000 |MEMINC EQU $4000 memory increment for 130's or EVM's
133 133 0000 2BFC |STKLEN EQU MEMINC-USERLEN-VECTSIZ-4 size of bug/diag stack + static vars
134 134 0000 |
135 135 0000 |*
136 136 0000 |* Interrupt levels & vectors
137 137 0000 |*
138 138 0000 0007 |ABORTLVL EQU 7 abort level
139 139 0000 001F |ABORTVEC EQU 31 abort vector
140 140 0000 0007 |ACFAILVL EQU 7 AC-Fail level
141 141 0000 0041 |ACFAILVC EQU 65 AC-Fail vector
142 142 0000 0006 |TIMERLVL EQU 6 timer level: M68332 periodic int. timer
143 143 0000 0042 |TIMERVEC EQU 66 timer vector
144 144 0000 |
145 145 0000 |*
146 146 0000 |* Setup Base Addresses:
147 147 0000 |* 1. A31-A24 must= 0 (MC68332 only uses A0-A23; rest are unused!)
148 148 0000 |* 2. A10-A0 must= 0 (for Base Address Register usage).
149 149 0000 |*
150 150 00FF F800 |ADDRMASK EQU $00FFF800 Address mask (24-bits, A10-A0= 0)
151 151 0000 0000 |RAM EQU RAM_BASE&ADDRMASK Setup Base Addresses
152 152 0006 0000 |ROM EQU ROM1_BASE&ADDRMASK Setup Base Addresses
153 153 0001 0000 |RAM2 EQU RAM2_BASE&ADDRMASK Setup Base Addresses
154 154 0008 0000 |ROM2 EQU ROM2_BASE&ADDRMASK Setup Base Addresses
155 155 00FF E800 |FPCP EQU FPCP_BASE&ADDRMASK Setup Base Addresses
156 156 0004 0000 |IRAM EQU IRAM_BASE&ADDRMASK Setup Base Addresses
157 157 00FF F800 |AVEC_7 EQU AUTO_BASE&ADDRMASK Setup Base Addresses
158 158 0000 |
159 159 0000 0000 |CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
160 160 0000 0000 |CSOR_XX EQU $0000 Reset (unused) value for CSORn
161 161 0000 |
162 162 FFFF FB00 |RAMMCR EQU RAMCR+$00 RAM Module Configuration Register
163 163 FFFF FB04 |RAMBAR EQU RAMCR+$04 RAM Module Base Address/Status Register
164 164 FFFF FA04 |SYNCR EQU SIM+$04 Clock Synthesizer Control Register
165 165 0000 4000 |VCO_X EQU $4000 VCO Frequency Control Bit X value
166 166 FFFF FA20 |SYPCR EQU SIM+$20 System Protection Control Register
167 167 FFFF FA44 |CSPAR EQU SIM+$44 Chip Select Pin Assignment Register
168 168 FFFF FA48 |CSBARBT EQU SIM+$48 Chip Select Base Boot Register
169 169 FFFF FA4A |CSORBT EQU SIM+$4A Chip Select Option Boot Register
170 170 FFFF FA4C |CSBAR0 EQU SIM+$4C Chip Select 0 Base Register
171 171 FFFF FA4E |CSOR0 EQU SIM+$4E Chip Select 0 Option Register
172 172 FFFF FA50 |CSBAR1 EQU SIM+$50 Chip Select 1 Base Register
173 173 FFFF FA52 |CSOR1 EQU SIM+$52 Chip Select 1 Option Register
174 174 FFFF FA54 |CSBAR2 EQU SIM+$54 Chip Select 2 Base Register
175 175 FFFF FA56 |CSOR2 EQU SIM+$56 Chip Select 2 Option Register
176 176 0000 |
177 177 0000 |*
178 178 0000 |* Option Register Equates (CSORBT, CSORn):
179 179 0000 |*
180 180 0000 0000 |B2K EQU 0 2K block size
181 181 0000 0001 |B8K EQU 1 8K block size
182 182 0000 0002 |B16K EQU 2 16K block size
183 183 0000 0003 |B64K EQU 3 64K block size
184 184 0000 0004 |B128K EQU 4 128K block size
185 185 0000 0005 |B256K EQU 5 256K block size
186 186 0000 0006 |B512K EQU 6 512K block size
187 187 0000 0007 |B1M EQU 7 1MB block size
188 188 0000 0000 |ASYNC EQU $0000 Asynchronous mode
189 189 0000 8000 |SYNC EQU $8000 Synchronous mode
190 190 0000 4000 |CS_UPPB EQU 2*$2000 Upper byte
191 191 0000 2000 |CS_LOWB EQU 1*$2000 Lower byte
192 192 0000 6000 |CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
193 193 0000 0800 |CS_R EQU 1*$800 Read
194 194 0000 1000 |CS_W EQU 2*$800 Write
195 195 0000 1800 |CS_RW EQU 3*$800 Read or write
196 196 0000 0000 |CS_AS EQU 0*$400 Address Strobe (AS*)
197 197 0000 0400 |CS_DS EQU 1*$400 Data Strobe (DS*)
198 198 0000 000E |CS_FAST EQU 14 Fast termination DSACK*
199 199 0000 000F |CS_EXT EQU 15 External termination DSACK*
200 200 0000 0040 |CS_WAIT EQU 1*$40 Wait cycles for DSACK*
201 201 0000 0000 |CS_CSP EQU 0*$10 CPU space
202 202 0000 0010 |CS_USP EQU 1*$10 User space
203 203 0000 0020 |CS_SSP EQU 2*$10 Supervisor space
204 204 0000 0030 |CS_SUSP EQU 3*$10 Supervisor/User space
205 205 0000 0002 |CS_LVL EQU 1*$2 Interrupt priority level
206 206 0000 0001 |CS_AVEC EQU 1 Autovector enable
207 207 0000 |
208 208 0000 |
209 209 0000 |******************************************************************************
210 210 0000 |*
211 211 0000 | SYSTEM
212 1m 0000 0001 +SECTD SET 1 ! DEFINE DATA SECTION
213 2m 0000 000E +SECTP SET 14 ! DEFINE PROGRAM SECTION
214 3m 0000 + SECTION SECTP ! PUT USER INTO PROG. SECTION
215 212 0000 |
216 213 0000 |* Start Chip Select Initialization:
217 214 0000 |*
218 215 0000 |INIT_CS:
219 216 0000 46FC 2700 | MOVE.W #SR_VAL,SR Ensure status register initialized.
220 217 0004 |
221 218 0004 |* Set up SYSTEM PROTECTION REGISTER:
222 219 0004 |*
223 220 0004 31FC 0006 | MOVE.W #6,SYPCR Turn off cop, DBF: BERR=16 clocks.
223 0008 FA20 |
224 221 000A |
225 222 000A |* Now let's go to 16.7 MHZ:
226 223 000A |*
227 224 000A 0078 4000 | OR.W #VCO_X,SYNCR X-bit doubles the current speed!
227 000E FA04 |
228 225 0010 |
229 226 0010 |* Remap Internal Standby RAM Module per CONFIGURATION PARAMETER values:
230 227 0010 |*
231 228 0010 323B 0170 | MOVE.W ((.RAMBAR).L,PC),D1 Get RAM Array Base Addr. value (RAMBAR).
231 0014 0000 0000 |
232 229 0018 0801 0000 | BTST #0,D1 . (Bit 0= RAMDS bit)
233 230 001C | IF <EQ> THEN.S If RAM Array Disabled Flag = OFF, then
234 1s 001C 6710 + BEQ.S .1
235 231 001E 303B 0170 | MOVE.W ((.RAMMCR).L,PC),D0 . Get RAM Module Config. Reg. value
235 0022 0000 0000 |
236 232 0026 31C0 FB00 | MOVE.W D0,RAMMCR . and put it in the register.
237 233 002A 31C1 FB04 | MOVE.W D1,RAMBAR . Put RAMBAR value into the register.
238 234 002E |* NOTE: RAMBAR can only be written once!
239 235 002E | ENDI
240 1s 002E +.1:
241 236 002E |
242 237 002E |* Enable SHOW CYCLES and allow INTERRRUPT ARBITRATION at priority 15:
243 238 002E |*
244 239 002E 0078 020F | OR.W #$020F,SIM Enable show cycles & external arb. @ 15
244 0032 FA00 |
245 240 0034 0278 DFFF | AND.W #$DFFF,SIM Clear FRZBM bit= when FREEZE bus moni-
245 0038 FA00 |
246 241 003A |* tor continues to operate as programmed.
247 242 003A |
248 243 003A |*
249 244 003A |* Set up all Chip Selects as "chip selects" in case user's have connected h/w
250 245 003A |* devices. Otherwise, address lines would be toggling as program runs and
251 246 003A |* possibly cause the devices to be enabled!
252 247 003A 21FC FFFF | MOVE.L #$FFFFFFFF,CSPAR All = chip selects, 16-bit port
252 003E FFFF FA44 |
253 248 0042 |* . (unused bits have no effect!)
254 249 0042 |
255 250 0042 |* Set up RAM and CSBOOT CHIP SELECTs to old BCC values:
256 251 0042 |*
257 252 0042 21FB 0170 | MOVE.L ((.CSBAR0).L,PC),CSBAR0
257 0046 0000 0000 |
257 004A FA4C |
258 253 004C 21FB 0170 | MOVE.L ((.CSBAR1).L,PC),CSBAR1
258 0050 0000 0000 |
258 0054 FA50 |
259 254 0056 21FB 0170 | MOVE.L ((.CSBARBT).L,PC),CSBARBT
259 005A 0000 0000 |
259 005E FA48 |
260 255 0060 |
261 256 0060 |* Test for old BBC by enabling its onboard RAM and ROM.
262 257 0060 |* If RAM found, then
263 258 0060 |* assume old BCC with old Platform Board
264 259 0060 |* else
265 260 0060 |* assume new BCC with new Platform Board
266 261 0060 |* endif
267 262 0060 |* If board == old_BCC
268 263 0060 |* initialize chip selects for old BCC and old platform board
269 264 0060 |* else
270 265 0060 |* initialize chip selects for new BCC and new platform board
271 266 0060 |* endif
272 267 0060 |*
273 268 0060 |* To find RAM:
274 269 0060 |* ($0000) = $5AA5A55A
275 270 0060 |* delay to allow bus capacitance to dissipate
276 271 0060 |* if ($0000) == $5AA5A55A then
277 272 0060 |* ($0000) = $A55A5AA5
278 273 0060 |* delay to allow bus capacitance to dissipate
279 274 0060 |* if ($0000) == $A55A5AA5 then
280 275 0060 |* RAM found
281 276 0060 |* endif
282 277 0060 |* else
283 278 0060 |* ($4000) = $5AA5A55A
284 279 0060 |* delay to allow bus capacitance to dissipate
285 280 0060 |* if ($4000) == $5AA5A55A then
286 281 0060 |* ($4000) = $A55A5AA5
287 282 0060 |* delay to allow bus capacitance to dissipate
288 283 0060 |* if ($4000) == $A55A5AA5 then
289 284 0060 |* RAM found
290 285 0060 |* endif
291 286 0060 |* endif
292 287 0060 |* endif
293 288 0060 |*
294 289 0060 |
295 290 0060 |* NOTE: By default at Power Up, CSBOOT responds to any address in the
296 291 0060 |* range of $0-$FFFFF (block size= 1 MB) to select the Boot ROM.
297 292 0060 |* Since the Boot ROM only uses address lines A0-A16 (128K), it
298 293 0060 |* appears replicated thru the memory map at every even ROM size
299 294 0060 |* ($20000) boundary as follows:
300 295 0060 |* $00000, $20000, $40000, $60000, $80000, $A0000, $C0000, $E0000
301 296 0060 |* Thus the power up reset vectors for the SP and PC are fetched from
302 297 0060 |* locations $0-7 and the PC is set to the memory range where we will
303 298 0060 |* be programming the Boot ROM to appear at via the chip selects.
304 299 0060 |* When the programming occurs, there are no addressing "glitches"
305 300 0060 |* because we stay at the same locations!
306 301 0060 |
307 302 0060 7001 | MOVEQ.L #NEW_BCC,D0
308 303 0062 223C 5AA5 | MOVE.L #$5AA5A55A,D1 NOTE: D1 and D2 are inverse patterns!
308 0066 A55A |
309 304 0068 243C A55A | MOVE.L #$A55A5AA5,D2
309 006C 5AA5 |
310 305 006E 91C8 | SUB.L A0,A0 Test loca. = $0000.
311 306 0070 |
312 307 0070 2081 | MOVE.L D1,(A0)
313 308 0072 | T_DELAY
314 1m 0072 4E71 + NOP
315 2m 0074 4E71 + NOP
316 3m 0076 4E71 + NOP
317 309 0078 | IF.L D1 <EQ> (A0) THEN.S If test loca. is good, then
318 1s 0078 B290 + CMP.L (A0),D1
319 2s 007A 6610 + BNE.S .2
320 310 007C 2082 | MOVE.L D2,(A0)
321 311 007E | T_DELAY
322 1m 007E 4E71 + NOP
323 2m 0080 4E71 + NOP
324 3m 0082 4E71 + NOP
325 312 0084 | IF.L D2 <EQ> (A0) THEN.S . If inverse is good, then
326 1s 0084 B490 + CMP.L (A0),D2
327 2s 0086 6602 + BNE.S .3
328 313 0088 7000 | MOVEQ.L #OLD_BCC,D0 . Got RAM, so must be old BCC!
329 314 008A | ENDI
330 1s 008A +.3:
331 315 008A | ELSE.S else maybe just 1 bad loca.
332 1s 008A 601E + BRA.S .4
333 2s 008C +.2:
334 316 008C 307C 4000 | MOVE.W #$4000,A0 . Test loca. = $4000.
335 317 0090 |*------------------------------------------------------------------------------
336 318 0090 |* CAUTION: In the above "MOVE.W #$XXXX,A0" do not use an address with the
337 319 0090 |* sign bit set, e.g., $8000, because sign extension will cause a
338 320 0090 |* BUS ERROR below and crash the system!
339 321 0090 |*------------------------------------------------------------------------------
340 322 0090 2081 | MOVE.L D1,(A0)
341 323 0092 | T_DELAY
342 1m 0092 4E71 + NOP
343 2m 0094 4E71 + NOP
344 3m 0096 4E71 + NOP
345 324 0098 | IF.L D1 <EQ> (A0) THEN.S . If test loca. is good, then
346 1s 0098 B290 + CMP.L (A0),D1
347 2s 009A 660E + BNE.S .5
348 325 009C 2082 | MOVE.L D2,(A0)
349 326 009E | T_DELAY
350 1m 009E 4E71 + NOP
351 2m 00A0 4E71 + NOP
352 3m 00A2 4E71 + NOP
353 327 00A4 | IF.L D2 <EQ> (A0) THEN.S . If inverse is good, then
354 1s 00A4 B490 + CMP.L (A0),D2
355 2s 00A6 6602 + BNE.S .6
356 328 00A8 7000 | MOVEQ.L #OLD_BCC,D0 . Got RAM, so must be old BCC.
357 329 00AA | ENDI
358 1s 00AA +.6:
359 330 00AA | ENDI
360 1s 00AA +.5:
361 331 00AA | ENDI
362 1s 00AA +.4:
363 332 00AA |
364 333 00AA 0C00 0000 | CMP.B #OLD_BCC,D0
365 334 00AE 6610 | BNE.S BCC_NEW Branch if old BCC not found!
366 335 00B0 |
367 336 00B0 |* Here for old BCC and old Platform board (see Rev. 1 schematics for each):
368 337 00B0 |*
369 338 00B0 |* U1/U3 = 120 nsec RAM w/fast termination
370 339 00B0 |* U2/U4 = ROM, but laid out wrong, so can only be used as 120 nsec RAM!
371 340 00B0 |*
372 341 00B0 |* CSBOOT = BCC U4 332Bug EPROM
373 342 00B0 |* CS0 = BCC U3 write enable for MSB=UPPER=EVEN ram
374 343 00B0 |* CS1 = BCC U2 write enable for LSB=LOWER=ODD ram
375 344 00B0 |* CS2 = PFB U1/U3 read enable for MSB/LSB=BOTH rams
376 345 00B0 |* CS3 = PFB U1 write enable for LSB=LOWER=ODD ram
377 346 00B0 |* CS4 = PFB U4 read enable for MSB=UPPER=EVEN rom
378 347 00B0 |* CS5 = PFB U2 read enable for LSB=LOWER=ODD rom
379 348 00B0 |* CS6 = PFB U5 chip enable for MC68881/882
380 349 00B0 |* CS7 = <unused>
381 350 00B0 |* CS8 = PFB ABORT pushbutton autovector
382 351 00B0 |* CS9 = <unused>
383 352 00B0 |* CS10 = PFB U3 write enable for MSB=UPPER=EVEN ram
384 353 00B0 |* . cut/jump U3-27 from CS4 to CS10 required!
385 354 00B0 |*
386 355 00B0 |* Set up other CHIP SELECT ports (CS0,CS1,CSBOOT already done):
387 356 00B0 |*
388 357 00B0 41FB 0170 |BCC_OLD LEA ((.CSBAR2).L,PC),A0 Point to old CS2 entry.
388 00B4 0000 0000 |
389 358 00B8 43F8 FA54 | LEA CSBAR2,A1 Point to corresponding SIM reg.
390 359 00BC 7008 | MOVEQ.L #(10-2+1)-1,D0 Set count to do CS2-CS10.
391 360 00BE |* . ("-1" for DBRA loop below!)
392 361 00BE 600E | BRA.S CS_COM Go to common init routine!
393 362 00C0 |
394 363 00C0 |
395 364 00C0 |* Here for new BCC and new Platform board (see Rev. 2 schematics for each):
396 365 00C0 |*
397 366 00C0 |* U1/U3 = 120 nsec RAM w/fast termination
398 367 00C0 |* U2/U4 = 250 nsec ROM (or jumper selectable as RAM)
399 368 00C0 |*
400 369 00C0 |* CSBOOT = BCC U4 332Bug EPROM
401 370 00C0 |* CS0 = BCC U3 write enable for MSB=UPPER=EVEN ram
402 371 00C0 |* CS1 = BCC U2 write enable for LSB=LOWER=ODD ram
403 372 00C0 |* CS2 = BCC U3/U2 read enable for MSB/LSB=BOTH rams
404 373 00C0 |* CS3 = <unused>
405 374 00C0 |* CS4 = PFB ABORT pushbutton autovector
406 375 00C0 |* CS5 = PFB U5 chip enable for MC68881/882
407 376 00C0 |* . cut/jump U5-J3 from CS2 to CS5 required!
408 377 00C0 |* CS6 = PFB U2 read enable for LSB=LOWER=ODD rom
409 378 00C0 |* CS7 = PFB U4 read enable for MSB=UPPER=EVEN rom
410 379 00C0 |* CS8 = PFB U1/U3 read enable for MSB/LSB=BOTH rams
411 380 00C0 |* CS9 = PFB U1 write enable for LSB=LOWER=ODD ram
412 381 00C0 |* CS10 = PFB U3 write enable for MSB=UPPER=EVEN ram
413 382 00C0 |*
414 383 00C0 |* Set up all CHIP SELECT ports (CSBOOT already done):
415 384 00C0 |*
416 385 00C0 41FB 0170 |BCC_NEW LEA ((CSBAR0$).L,PC),A0 Point to new CS0 entry.
416 00C4 0000 0000 |
417 386 00C8 43F8 FA4C | LEA CSBAR0,A1 Point to corresponding SIM reg.
418 387 00CC 700A | MOVEQ.L #(10-0+1)-1,D0 Set count to do CS0-CS10.
419 388 00CE |* . ("-1" for DBRA loop below!)
420 389 00CE |
421 390 00CE |* Common CHIP SELECTS initialization routine:
422 391 00CE |* A0.L = chip select configuration table entry (base addr)
423 392 00CE |* A1.L = corresponding SIM register
424 393 00CE |* D0.W = number of chip selects -1 to be initialized
425 394 00CE |*
426 395 00CE 22D8 |CS_COM MOVE.L (A0)+,(A1)+ Init. SIM base addr + option register.
427 396 00D0 51C8 FFFC | DBRA D0,CS_COM Continue until all regs init'ed.
428 397 00D4 |
429 398 00D4 60FF 0000 | BRA.L PWR_TTL Return to Power On Branch Vector
429 00D8 0000 |
430 399 00DA | END
430 lines assembled
symbol table:
symbol name attrib. section value
----------- ------- ------- -----
INIT_CS .text 14 0x0
@218 @61
PWR_TTL xref
429 @64
.RAMMCR xref
235 @65
.RAMBAR xref
231 @66
.CSBAR0 xref
257 @67
.CSBAR1 xref
258 @67
.CSBAR2 xref
388 @67
.CSBARBT xref
259 @67
CSBAR0$ xref
416 @68
SYSTEM macro
211
T_DELAY macro
349 341 321 313
OLD_BCC abs. 0x0
364 356 328 @91
NEW_BCC abs. 0x1
307 @92
SR_VAL abs. 0x2700
219 @100
RAM_BASE abs. 0x0
151 113 @102
RAM_SIZE abs. 0x10000
115 @103
ROM1_BASE abs. 0x60000
152 128 120 @104
ROM1_SIZE abs. 0x20000
128 @105
IRAM_BASE abs. 0x40000
156 @106
FPCP_BASE abs. 0xffffe800
155 @107
SIM abs. 0xfffffa00
245 244 175 174 173 172 171 170 169 168
167 166 164 @109
RAMCR abs. 0xfffffb00
163 162 @110
AUTO_BASE abs. 0xfffff800
157 @111
LOCALRAM abs. 0x0
127 118 116 @113
SYSRAMSZ abs. 0x4000
117 116 @114
LCLRAMMX abs. 0x10000
127 117 @115
USRRAM abs. 0x4000
@116
USRRAMSZ abs. 0xc000
@117
RAMSTART abs. 0x0
@118
LOCALROM abs. 0x60000
@120
LCLROMSZ abs. 0x10000
@121
ROMUNPGM abs. 0xff
123 @122
FILL.1 abs. 0xff
124 124 @123
FILL.2 abs. 0xffff
125 125 @124
FILL.4 abs. 0xffffffff
@125
RAM2_BASE abs. 0x10000
153 @127
ROM2_BASE abs. 0x80000
154 @128
VECTSIZ abs. 0x400
133 @130
USERLEN abs. 0x1000
133 @131
MEMINC abs. 0x4000
133 @132
STKLEN abs. 0x2bfc
@133
ABORTLVL abs. 0x7
@138
ABORTVEC abs. 0x1f
@139
ACFAILVL abs. 0x7
@140
ACFAILVC abs. 0x41
@141
TIMERLVL abs. 0x6
@142
TIMERVEC abs. 0x42
@143
ADDRMASK abs. 0xfff800
157 156 155 154 153 152 151 @150
RAM abs. 0x0
@151
ROM abs. 0x60000
@152
RAM2 abs. 0x10000
@153
ROM2 abs. 0x80000
@154
FPCP abs. 0xffe800
@155
IRAM abs. 0x40000
@156
AVEC_7 abs. 0xfff800
@157
CSBAR_XX abs. 0x0
@159
CSOR_XX abs. 0x0
@160
RAMMCR abs. 0xfffffb00
236 @162
RAMBAR abs. 0xfffffb04
237 @163
SYNCR abs. 0xfffffa04
227 @164
VCO_X abs. 0x4000
227 @165
SYPCR abs. 0xfffffa20
223 @166
CSPAR abs. 0xfffffa44
252 @167
CSBARBT abs. 0xfffffa48
259 @168
CSORBT abs. 0xfffffa4a
@169
CSBAR0 abs. 0xfffffa4c
417 257 @170
CSOR0 abs. 0xfffffa4e
@171
CSBAR1 abs. 0xfffffa50
258 @172
CSOR1 abs. 0xfffffa52
@173
CSBAR2 abs. 0xfffffa54
389 @174
CSOR2 abs. 0xfffffa56
@175
B2K abs. 0x0
@180
B8K abs. 0x1
@181
B16K abs. 0x2
@182
B64K abs. 0x3
@183
B128K abs. 0x4
@184
B256K abs. 0x5
@185
B512K abs. 0x6
@186
B1M abs. 0x7
@187
ASYNC abs. 0x0
@188
SYNC abs. 0x8000
@189
CS_UPPB abs. 0x4000
@190
CS_LOWB abs. 0x2000
@191
CS_BOTHB abs. 0x6000
@192
CS_R abs. 0x800
@193
CS_W abs. 0x1000
@194
CS_RW abs. 0x1800
@195
CS_AS abs. 0x0
@196
CS_DS abs. 0x400
@197
CS_FAST abs. 0xe
@198
CS_EXT abs. 0xf
@199
CS_WAIT abs. 0x40
@200
CS_CSP abs. 0x0
@201
CS_USP abs. 0x10
@202
CS_SSP abs. 0x20
@203
CS_SUSP abs. 0x30
@204
CS_LVL abs. 0x2
@205
CS_AVEC abs. 0x1
@206
SECTD abs. 0x1
@212
SECTP abs. 0xe
214 @213
.1 .text 14 0x2e
@240 234
.2 .text 14 0x8c
@333 319
.3 .text 14 0x8a
@330 327
.4 .text 14 0xaa
@362 332
.5 .text 14 0xaa
@360 347
.6 .text 14 0xaa
@358 355
BCC_NEW .text 14 0xc0
@416 365
BCC_OLD .text 14 0xb0
@388
CS_COM .text 14 0xce
427 @426 392
.text section 14
110 symbols